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LMZ14203EXT
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I LR P-P = V O *(V IN - V O )/(6.8μH*f SW *V IN )
where
SNVS666F – JUNE 2010 – REVISED OCTOBER 2013
?
V IN is the maximum input voltage
?
f SW is determined from Equation 7
(14)
If the output current I O is determined by assuming that I O = I L , the higher and lower peak of I LR can be
determined. Be aware that the lower peak of I LR must be positive if CCM operation is required.
POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS
For the design case of V IN = 24V, V O = 3.3V, I O = 3A, T AMB(MAX) = 85°C , and T JUNCTION = 125°C, the device must
see a thermal resistance from case to ambient of:
θ CA < (T J-MAX — T AMB(MAX) ) / P IC-LOSS - θ JC
(15)
Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves
in the Typical Performance Characteristics section to estimate the P IC-LOSS for the application being designed. In
this application it is 2.25W.
θ CA < (125 — 85) / 2.25W — 1.9 = 15.8
To reach θ CA = 15.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:
Board Area_cm 2 > 500°C x cm 2 /W / θ CA
(16)
As a result, approximately 31.5 square cm of 1 oz copper on top and bottom layers is required for the PCB
design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8mils thermal
vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high
thermal performance PCB layout, refer to the Evaluation Board application note AN-2024 SNVA422 .
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
V IN
VIN
LMZ14203EXT
VOUT
V O
High
C in1
Loop 1
di/dt
GND
Loop 2
C O1
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout. The
high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on
the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14203EXT. Therefore place
C IN1 as close as possible to the LMZ14203EXT VIN and GND exposed pad. This will minimize the high di/dt area
and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a
localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of
the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly
handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide
the single point ground connection from pin 4 to EP.
Copyright ? 2010–2013, Texas Instruments Incorporated
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